The present invention relates to analog-to-digital converters (ADCs), in particular to accuracy enhancement thereof.
ADCs convert an input analog signal to a digital representation (e.g., digital word). A successive approximation register (SAR) ADC, a type of ADC, converts an input analog signal to a digital representation using a series of bit trials performed sequentially from a most-significant bit (MSB) to a least-significant bit (LSB). In each bit trial, a comparator compares the input analog signal to a reference voltage and based on the comparator decisions, the respective bit is resolved as either a ‘1’ or ‘0’. Errors, however, can enter the conversion process, referred to as the conversion error of the SAR ADC. Typically, the larger the conversion error, the worse the signal-to-noise ratio (SNR) of the ADC.
Conversion errors can take various forms. For example, after the SAR ADC resolves the LSB, an error voltage may be present at the input of the comparator, often referred to as a residue input. This residue input may represent the conversion error of the SAR ADC and can include quantization errors, circuit noise, etc. Conventional approaches to reducing conversion errors include resolving smaller bits to reduce quantization errors or tuning components to reduce circuit noise; however, these approaches come at high costs in terms of speed, power consumption, and/or circuit area.
Therefore, the inventors recognized a need in the art for accuracy enhancement techniques to improve ADC SNRs without the aforementioned costs.